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Tuesday, May 10, 2011

Low-Power Design

           Building wireless systems for low-power operation is one of the most important and challenging design goals. While low power is a design goal for almost all wireless systems, it is an especially challenging boundary condition for 3G systems. This is due to two issues: First, the power amplifier (PA), which determines to a large extent the talk-time of present terminals, has to cope with a linear modulation format (basically QPSK) in 3G systems.
Therefore, the RF envelope shows high amplitude variations, which requires a linear PA operation over a wide amplitude range that is only possible with low efficiency. In general, low-power design is a multi-disciplinary problem since transceiver architecture and circuit design determine the instantaneous power consumption, while the average power consumption depends to a large extent also on a good power management at the system and protocol levels. The RF PA in the transmitter front-end is the dominant power consumption block in any wireless communication system.
        Integration of RF and Base band Functionalities

A steadily increasing level of integration will probably lead to single-chip transceiver solutions. This includes also the integration of the analog front-end with the digital base band part. There are many obstacles like, e.g., interference due to substrate coupling, different supply voltage requirements, heat dissipation problems, pin count, etc., but benefits like reduced component count and required printed circuit board area as well as enhanced functionality can be attained.

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