Next we apply a difference or differential input voltage by grounding the gate of

**(i.e.,setting***Q2***= 0) and applying a signal***v*_{G2}*v***to the gate of**_{id}**as shown in Fig. 2.3. It is easy to see that since***Q1**v*_{id}=v_{GS1}-v_{GS2 }, if*v*_{id}_{ }is positive,**will be greater than***V*_{GSl}*v***and hence**_{Gs2}*i*_{D1}_{ }will be greater than**and the difference output voltage (***i*_{D2}*v***-**_{D2}*v***) will be positive. On the other hand, when**_{D2}*v***is negative,**_{id}*v***will be lower than**_{GS1}*v*_{GS2}_{ },**will be smaller than***i*_{D1}**, and correspondingly***i*_{D2}*v***will be higher than**_{D1}*v***; in other words, the difference or differential output voltage (**_{D2}*v***-**_{D2}*v***) will be negative.**_{D1}**Fig. 2.3**The MOS differential pair with a differential input signal v

_{id}applied. With v

_{id}positive: v

_{GS1}> v

_{GS2 ,}and v

_{D1}<v

_{D2}thus thus (v

_{D2}-v

_{D1}) will be positive. With v

_{id}negative: v

_{GS1}< v

_{GS2}, i

_{D1}< i

_{D2}and (v

_{D1}>v

_{D2 }) thus (v

_{D2}-v

_{D1}) will be negative.

From the above, we see that the differential pair responds to difference-mode or differential input signals by providing a corresponding differential output signal between the two drains. At this point, it is useful to inquire about the value of

**that causes the entire bias current I to flow in one of the two transistors. In the positive direction, this happens when***v*_{id}**reaches the value that corresponds to***v*_{GS1}**=***i*_{D1}**and***I,**v*_{GS2}_{ }is reduced to a value equal to the threshold voltage**, at which point***V*_{t}**=-***v*_{s}**The value of***V*_{t}**can be found from***v*_{GS1}
where

**is the overdrive voltage corresponding to a drain current of***V*_{OV}**(Eq. 2.5). Thus the value of***1/2***at which the entire bias current***v*_{id}**is steered into***I***إس***Q1*
, and

,

**rises correspondingly, thus keeping***v*_{S}**off. In a similar manner we can show that in the negative direction, as v***Q2*_{id}reaches,

**turns off and***Q1***conducts the entire bias current***Q2***.***I*
Thus the current

**can be steered from one transistor to the other by varying***I***din the range***v*_{id}
which defines the range of differential-mode operation. Finally, observe that we have assumed that

**and***Q1***remain in saturation even when one of them is conducting the entire current***Q2***.***I*
To use the differential pair as a linear amplifier, we keep the differential input signal

proportional to

Simultaneously, the current in the other transistor will decrease by the same amount to become

, develops at the other drain. Thus the output voltage taken between the two drains will be

**small. As a result, the current in one of the transistors (***v*_{id}**when***Q1***is positive) will increase by an increment***v*_{id}proportional to

**to***v*_{id}Simultaneously, the current in the other transistor will decrease by the same amount to become

A voltage signal

develops at one of the drains and an opposite-polarity signal, , develops at the other drain. Thus the output voltage taken between the two drains will be

_{ }, which is proportional to the differential input signal**. The small-signal operation of the differential pair .***v*_{id}**FIGURE 2.5**The MOSFET differential pair for the purpose of deriving the transfer characteristics, i

_{D1}and i

_{D1}versus

*v*_{id=}v_{G1 }-v_{G2}_{ }.