To see how the differential pair works, consider first the case of the two gate terminals

interjoined together and connected to a voltage

interjoined together and connected to a voltage

*v*CM called the common-mode voltage. That is as shown in Fig (2.2)
Since Ql and Q2 are matched, it follows from symmetry that the current I will divide equally between the two transistors. Thus

and the voltage at the sources, *v*s will be
where V

_{GS}is the gate-to-source voltage corresponding to a drain current of I/2. Neglecting channel-length modulation, VGs and I/2 are related by
or in terms of the overdrive voltage

The voltage at each drain will be

Thus, the difference in voltage between the two drains will be zero.

**Fig. 2.2**

**The MOS differential pair with a common-mode input voltage**

Now, let us vary the value of the common-mode voltage

*v*_{CM}_{ }Obviously, as long as*Q1*and*Q2*remain in the saturation region, the current*I*will divide equally between*Q1*and*Q2*and the voltages at the drains will not change. Thus the differential pair does not respond to (i.e., it rejects) common-mode input signals.
An important specification of a differential amplifier is its input common-mode range.This is the range of

*v**over which the differential pair operates properly. The highest value of*_{CM}*v**is limited by the requirement that*_{CM}*Q1*and*Q2*remain in saturation, thus
The lowest value of

*v***is determined by the need to allow for a sufficient voltage across current source I for it to operate properly. If a voltage**_{CM}*V***is needed across***cs*
the current source, then