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Tuesday, May 10, 2011

CMOS vs Cost Reduction

  Cost reduction is a major tenet of CMOS. The primary factor underlying the decreasing cost per circuit is the increase in density, or circuits per square millimeter. The cost of processing a silicon wafer must increase much less rapidly than the density in order to achieve cost reduction. The rapid (25% per year) increase during the 1980s of the capital cost of a silicon manufacturing line led to concerns of diminishing returns in cost per circuit. However, since 1990 the rate of increase has slowed to less than 15% a year. Major factors behind this reduction were a stabilization of clean-room requirements, better equipment productivity and utilization, and a slower increase in the number of process steps. The dominant cost factor in producing integrated circuits is the capital cost for the clean-room building and the equipment. The rate of increase of these costs must be matched by a greater rate of increase of components per chip. As long as the increase in components per chip is utilized by effective designs providing more function for the user, the industry will continue to thrive.
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