Next we apply a difference or differential input voltage by grounding the gate of Q2 (i.e.,setting vG2 = 0) and applying a signal vid to the gate of Q1 as shown in Fig. 2.3. It is easy to see that since vid=vGS1-vGS2 , if vid is positive, VGSl will be greater than vGs2 and hence iD1 will be greater than iD2 and the difference output voltage (vD2-vD2) will be positive. On the other hand, when vid is negative, vGS1 will be lower than vGS2 , iD1 will be smaller than iD2, and correspondingly vD1 will be higher than vD2; in other words, the difference or differential output voltage (vD2-vD1) will be negative.
Fig. 2.3 The MOS differential pair with a differential input signal vid applied. With vid positive: vGS1 > vGS2 , and vD1<vD2 thus thus (vD2-vD1) will be positive. With vid negative: vGS1 < vGS2, iD1< iD2 and (vD1>vD2 ) thus (vD2-vD1) will be negative.
From the above, we see that the differential pair responds to difference-mode or differential input signals by providing a corresponding differential output signal between the two drains. At this point, it is useful to inquire about the value of vid that causes the entire bias current I to flow in one of the two transistors. In the positive direction, this happens when vGS1 reaches the value that corresponds to iD1= I, and vGS2 is reduced to a value equal to the threshold voltage Vt, at which point vs=-Vt The value of vGS1 can be found from
where VOV is the overdrive voltage corresponding to a drain current of 1/2 (Eq. 2.5). Thus the value of vid at which the entire bias current I is steered into Q1 إس
if vid is increased beyond
, iD1 remains equal to I, vGS1 remains equal to
, and vS rises correspondingly, thus keeping Q2 off. In a similar manner we can show that in the negative direction, as vid reaches
,Q1 turns off and Q2 conducts the entire bias current I.
Thus the current I can be steered from one transistor to the other by varying vid din the range
which defines the range of differential-mode operation. Finally, observe that we have assumed that Q1 and Q2 remain in saturation even when one of them is conducting the entire current I.
To use the differential pair as a linear amplifier, we keep the differential input signal vid small. As a result, the current in one of the transistors (Q1 when vid is positive) will increase by an increment
proportional to vid to
Simultaneously, the current in the other transistor will decrease by the same amount to become
develops at one of the drains and an opposite-polarity signal,
, develops at the other drain. Thus the output voltage taken between the two drains will be
, which is proportional to the differential input signal vid. The small-signal operation of the differential pair .
A voltage signal
FIGURE 2.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD1 versus vid=vG1 -vG2 .
