CMOS NOR gate

The realization of a two-input CMOS NOR gate is shown Fig 4.4. For the  NOR gate, The output should be low when either input A or input B is high. Thus the NMOS portion of the gate is identical to that of the NMOS NOR gate. However, in the CMOS gate, we must ensure that a static current path does not exist through the logic gate, and this requires the use of two PMOS transistors in series in the PMOS transistor network.

Fig 3.4. NOR circuit diagram.

The complementary nature of the conducting paths can be seen in Table 3.3.A conducting path exists through the NMOS network for V1 = 1 or V2 =1 However, a path exists through the PMOS network only when both V1 = 0 and V2 = 0 (no conducting path through the NMOS network).

(a)

 (b)

 (c)

Fig 3.5. NOR input output voltages. (a) Input voltage (v₁) (b)  Input voltage (V₂)

        (c)  Output voltage (V_out)

Table 3.3   CMOS NOR Gate Truth Table and Transistor States

CMOS NOR Gate Truth Table and Transistor States

References

" CMOS NOR gate " !

Inverter Delay Time and Power Dissipation

The inverter delay time can be calculated as follows

Fig. 3.a shows inverter delay time as a function of the channel length. It shows that the delay time decreases as the channel length decreases.

Fig. 3.a. Variation of the inverter delay time as a function of channel length 

 

The inverter power dissipation can be expressed as follows

Fig. 3.b shows the variation of the inverter power dissipation as a function of supply voltage. The power dissipation decreases as the supply voltage decreases.

Fig. 3.b. Variation of the inverter power dissipation as  a function of supply voltage.

References

" Inverter Delay Time and Power Dissipation " !

Inverter

The CMOS logic gate can be conceptually modeled by the circuit in Fig 3.1, in which the position of the two switches is controlled by the input voltage v_i. The circuit is designed so there will never be a conducting path between the positive and negative power supplied under steady –state conditions. When the NMOS transistor is on, the PMOS transistor is off; if the PMOS transistor is on, the NMOS device is off.

Fig 3.1. Inverter circuit diagram

In the CMOS inverter of Fig 3.1,  the source of the PMOS transistor is connected to V_DD , the source of the NMOS transistor is connected to V_SS (0 V in this case), and the drain terminals of the two MOSFETs are connected together to form the output node. Also the substrates of both the NMOS and PMOS transistors are connected to their respective sources, and so body effect is eliminated in both devices.

(a)

 (b)

Fig 3.2.  Inverter input output voltages, (a) Input voltage.  (b) Output voltage

Table 3.1 CMOS Inverter truth table and transistor states

    CMOS Voltage Transfer characteristics            

Figure 3.3 shows the voltage transfer characteristic (VTC) of the Symmetrical CMOS inverter, designed with K_p=K_N . The VTC can be divided into five different regions, as shown in the figure and summarized in table 3.2. For an input voltage less than V_TN = 1V in region 1, the NMOS transistor is off, and the output is maintained at V_OH = 5V by the PMOS device.

Similarly, for an input voltage greater than (V_DD - | V_TP | )(4 V) in region 5, the PMOS device is off, and the output is maintained at V_0L = 0V by the NMOS transistor. In region 2, the NMOS transistor is saturated, and the PMOS transistor is in the linear region. In region 3, both transistors are saturated. The boundary between regions 2&3 defined by the boundary between the saturation and linear region of operation for the PMOS transistor. Saturation of the PMOS device requires:

Table 3.2 Regions of operation of transistors in a symmetrical CMOS inverter

In a similar manner, the boundary between regions 3 and 4 is defined by saturation of the NMOS device:

 

In region 4, the voltage place the NMOS transistor in the linear region, and the PMOS transistor remains saturated. Finally, for the input voltage near V_DD/2   (region 3), both transistors are operating in the saturation region.

By using small channel length, produce increase in cut – off frequency so delay time decreased and this increase speed of operation.

 

Also me advantages of using small channel length:

1- decreasing tsohreshold voltage

2- decreasing supply voltage

3- decreasing palter dissipation

References

" Inverter " !

CMOS Logic Circuits

For many years, complementary MOS (CMOS) technology was available only in unit logic form, with several gates packaged together in a single dual in – line package (DIP), but it was not widely used in complex integrated circuits. CMOS requires that both NMOS and PMOS transistors be built into the same substrate, and the increased complexity and cost this represents were the primary reasons why CMOS technology was little used .as time passed ,however ,the size of transistors in ICs continued to decrease, so an ever – larger number of gates could be placed on a given size IC chip. By the early 1980s, the total power consumption of NMOS ICs was becoming prohibitive. The problem was so severe that it was hampering progress in increasing the density of ICs. To solve the static power dissipation problem, the microprocessor industry at this point rapidly moved to CMOS technology. Today, CMOS is the industry wide standard technology.

This chapter investigates the design of CMOS logic circuits, starting with characterization of the CMOS inverter, and follows with a discussion of the design of NOR,NAND,and complex gates  based on  CMOS reference inverter . 

" CMOS Logic Circuits " !