The realization of a two-input CMOS NOR gate is shown Fig 4.4. For the NOR gate, The output should be low when either input A or input B is high. Thus the NMOS portion of the gate is identical to that of the NMOS NOR gate. However, in the CMOS gate, we must ensure that a static current path does not exist through the logic gate, and this requires the use of two PMOS transistors in series in the PMOS transistor network.
Fig 3.4. NOR circuit diagram.
The complementary nature of the conducting paths can be seen in Table 3.3.A conducting path exists through the NMOS network for V1 = 1 or V2 =1 However, a path exists through the PMOS network only when both V1 = 0 and V2 = 0 (no conducting path through the NMOS network).
(a)
(b)
(c)
The complementary nature of the conducting paths can be seen in Table 3.3.A conducting path exists through the NMOS network for V1 = 1 or V2 =1 However, a path exists through the PMOS network only when both V1 = 0 and V2 = 0 (no conducting path through the NMOS network).
(b)
Fig 3.5. NOR input output voltages. (a) Input voltage (v1) (b) Input voltage (V2)
(c) Output voltage (Vout)
Table 3.3 CMOS NOR Gate Truth Table and Transistor States
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| CMOS NOR Gate Truth Table and Transistor States |
