Typical values for the important parameters of NMOS and PMOS transistors fabricated in a number of CMOS processes are shown in this Table 1.2.
Table 1.2 parameters of NMOS and PMOS transistors
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| Parameters of NMOS and PMOS transistors |
As indicated in Table, the trend has been to reduce the minimum allowable channel length. This trend has been motivated by the desire to pack more transistor on a chip as well as to operate at higher speeds or, in analog terms, over wider bandwidths. Although the magnitudes of the threshold voltages Vtn and Vtp have been decreasing with Lmin, from about 0.7 ~ 0.8 V to 0.4 ~ 0.5 V, the reduction has not been as large as that of the power supply VDD. The latter has been reduced dramatically, from 5V for older technology to 1.8 V for .18µm. This reduction has been necessitated by the need to keep the electric fields in the smaller devices from reaching very high values.
Another reason for reducing VDD is to keep power dissipation as low as possible given that the IC chip now has a much larger number of transistors. We find high cut frequency response of the common-source amplifier and higher operating speeds and wider amplifier bandwidths than the longer device, for example, see that for a 0.25-µm NMOS transistor can be as high as 10 GHz.
a) Advantages
1) The major advantages of silicon gate CMOS ICs are their higher speed and lower power consumption. These features impact a broad range of device performance parameters. A faster chip widens the scope of possible applications and increases signal quality and reliability. For a given frequency response, power can be reduced. The CMOS ICS can respond to higher frequency inputs, the timers can oscillate at higher frequencies, and the response times of operational amplifiers and comparators are reduced while slew rate and operating frequency increase. All of these qualities give wider signal frequency range and operating and design margin providing increased accuracy and gain bandwidth at reduced voltages and power requirement over broad operating conditions.
2) The low power consumptions of CMOS chips is advantageous in a number of different ways. Many devices can operate at supply voltages as low as 1V and with ultra low leakage current which facilitates battery operation. This not only means less power consumption, but for operational amplifiers and comparators it results in a lower offset voltage caused by thermal drift and for timers it results in higher accuracy and stability. This lessens the dependence of timing accuracy on expensive components, increasing the accuracy and reducing the cost of the timing function. In addition, as the number of transistors per chip increases, the low power consumption of CMOS Ics allow greater densities but will require little or no external cooling and very little self-heating design considerations.
3) Another advantage of silicon gate CMOS linear technology to be discussed here is its compatibility with CMOS digital technology. The availability and relative ease with which digital functions such as logic gates, flip-flops, counters and memory cells can be added to the analog library means that complete systems, including a large amount of digital logic, analog modules, and passive components such as resistors and capacitors, can all be integrated into one ASIC chip. This capability is referred to as mixed mode (analog and digital) integration where most components of an electronic system are implemented in a single monolithic IC chip. Generally, in a given system only a few other types of components such as transducers, sensors, inductors, precision resistors, large capacitors, relays, etc. are left off the IC chip.
4) The final advantage of CMOS linear technology is high circuit function density as shown in Fig 1.4 and low cost. As CMOS linear technology is a VLSI (very large scale integration) technology, many circuit function blocks can be integrated onto the same monolithic IC chip, not only producing compactness, and system miniaturization, but also producing low per function cost and high per function reliability. Furthermore, due to integration of large number of elements, board area cost, labor cost and inventory management costs are greatly reduced.
