Amplitude Modulation ( AM )

Amplitude modulation is used since the first days of the 20th century mainly for transmitting voice and signals through the conventional broadcast band like the long-, medium- and short wave bands because of its easy and cheap way of realisation.

Besides the consumption of bandwidth in comparison to usual FM is relatively small and the receivers could be made up very simple.

Standard AM system

AM is an important method for transmitting information. We shall state the circuits used in the modulation and demodulation of the AM signals.

References
 

" Amplitude Modulation ( AM ) " !

CMOS NOR gate

The realization of a two-input CMOS NOR gate is shown Fig 4.4. For the  NOR gate, The output should be low when either input A or input B is high. Thus the NMOS portion of the gate is identical to that of the NMOS NOR gate. However, in the CMOS gate, we must ensure that a static current path does not exist through the logic gate, and this requires the use of two PMOS transistors in series in the PMOS transistor network.

Fig 3.4. NOR circuit diagram.

The complementary nature of the conducting paths can be seen in Table 3.3.A conducting path exists through the NMOS network for V1 = 1 or V2 =1 However, a path exists through the PMOS network only when both V1 = 0 and V2 = 0 (no conducting path through the NMOS network).

(a)

 (b)

 (c)

Fig 3.5. NOR input output voltages. (a) Input voltage (v₁) (b)  Input voltage (V₂)

        (c)  Output voltage (V_out)

Table 3.3   CMOS NOR Gate Truth Table and Transistor States

CMOS NOR Gate Truth Table and Transistor States

References

" CMOS NOR gate " !

Circuits Used in the Amplitude Modulation

Amplitude and Balanced Modulation

Amplitude modulation is a technique which uses a low-frequency signal to control the amplitude of a high- frequency signal. A simple modulator can be constructed using a multiplier as shown in figure 5.2.

Figure 5.2 A simple amplitude modulator circuit.

One input is the high-frequency or carrier signal, and the other input is the modulating signal. A sinusoidal source at a frequency of 10 kHz is used to represent the carrier signal and a second source at a frequency of 1 kHz is used to represent the modulating signal. Notice that the peak amplitude for the carrier is set to 1 volt using the parameter VcarrierPK. The modulating index is the ratio of the peak of the modulating signal to the peak of the carrier. Here, the index is set to 0.8 or 80% modulation. A typical broadcast AM signal includes the carrier as well as the sidebands in the transmission. To get such a double sideband transmitted carrier signal (DSB-TC) we must bias or offset the modulating signal by a value equal to the carrier's peak voltage. The amplitude modulated signal and the modulating signal from this simulation are shown in figure 5.3.

Figure 5.3 An amplitude modulator output signal.

      A balanced modulator produces a double sideband suppressed carrier signal (DSB-SC). By setting the offset of the modulating signal to be zero in the above circuit, we will suppress the carrier. Notice, the output of this modulator shown in figure 5.4; the shape of its upper A balanced modulator output signal envelope resembles a full-wave rectified AC source.

Figure 5.4 A balanced modulator output signal

     By using a specific OTA                       

    ( Operational transconductance amplifier )

      The LM13700 is a typical OTA and serves as a representative device. The LM13700 is a dual-device package containing two OTAs and buffer circuits. Figure 5.5 shows the pin configuration using a single OTA in the package. The maximum dc supply voltages are +18v and  -18v .

 For an LM13700, the bias current is determined by the following formula:

The 1.4 v is due to the internal circuit where a base-emitter junction and a diode connect the external Rbias with the negative supply voltage (-V). The positive bias voltage, +Vbias, may be obtained from the positive supply voltage, +V.

 Fig. 5.5

    Two OTA Applications                   

Amplitude modulator…….Figure 5.6 illustrates an OTA connected as an amplitude modulator. The voltage gain is varied by applying a modulation voltage to the bias input. When a constant-amplitude input signal is applied, the amplitude of the output signal will vary according to the modulation voltage on the bias input. The gain is dependent on bias current, and bias current is related to the modulation voltage by the following relationship:

This modulating action is shown in fig 5.6 for a higher-frequency sinusoidal input voltage and a lower-frequency sinusoidal modulating voltage.

Figure 5.6 The OTA as an amplitude modulator.

     References
     

" Circuits Used in the Amplitude Modulation " !

How to Convert Analog Signal Into Digital One

In order to make analog to digital conversion we should convert the analog signal into digital by sampling and quantization processes ( Pulse Code Modulation) .

         Sampling of Analog Signals                    

       The principle underlying digital signal processing is that of sampling the analog signal Fig 4.2 illustrates in a conceptual form the process of obtaining samples of an analog signal. The switch shown closes periodically under the control of a periodic pulse signal (clock). The closure time of the switch, τ, is relatively short, and the samples obtained are stored (held) on the capacitor. The circuit of the following figure is known as a sample-and-hold (S/H) Circuit. As indicated, the S/H circuit consists of an analog switch that can be implemented by a MOSFET transmission gate. A storage capacitor, and (not shown) a buffer amplifier.

Between the sampling intervals-that is, during the hold intervals-the voltage level on the capacitor represents the signal sample we are after. Each of these voltage levels is then fed to the input of an A/D converter, which provides an N-bit binary number proportional to the value of signal sample. The fact that we can do our processing on a limited number of samples of an analog signal while ignoring the analog-signal details between samples is based on the shannon’s sampling theorem

Fig 4.2  The process of periodically sampling an analog signal (a) Sample-and-hold (S/H) circuit The switch closes for a small part of time of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Out put signal (to be fed to A/D converter).

References

" How to Convert Analog Signal Into Digital One " !

Inverter Delay Time and Power Dissipation

The inverter delay time can be calculated as follows

Fig. 3.a shows inverter delay time as a function of the channel length. It shows that the delay time decreases as the channel length decreases.

Fig. 3.a. Variation of the inverter delay time as a function of channel length 

 

The inverter power dissipation can be expressed as follows

Fig. 3.b shows the variation of the inverter power dissipation as a function of supply voltage. The power dissipation decreases as the supply voltage decreases.

Fig. 3.b. Variation of the inverter power dissipation as  a function of supply voltage.

References

" Inverter Delay Time and Power Dissipation " !

Inverter

The CMOS logic gate can be conceptually modeled by the circuit in Fig 3.1, in which the position of the two switches is controlled by the input voltage v_i. The circuit is designed so there will never be a conducting path between the positive and negative power supplied under steady –state conditions. When the NMOS transistor is on, the PMOS transistor is off; if the PMOS transistor is on, the NMOS device is off.

Fig 3.1. Inverter circuit diagram

In the CMOS inverter of Fig 3.1,  the source of the PMOS transistor is connected to V_DD , the source of the NMOS transistor is connected to V_SS (0 V in this case), and the drain terminals of the two MOSFETs are connected together to form the output node. Also the substrates of both the NMOS and PMOS transistors are connected to their respective sources, and so body effect is eliminated in both devices.

(a)

 (b)

Fig 3.2.  Inverter input output voltages, (a) Input voltage.  (b) Output voltage

Table 3.1 CMOS Inverter truth table and transistor states

    CMOS Voltage Transfer characteristics            

Figure 3.3 shows the voltage transfer characteristic (VTC) of the Symmetrical CMOS inverter, designed with K_p=K_N . The VTC can be divided into five different regions, as shown in the figure and summarized in table 3.2. For an input voltage less than V_TN = 1V in region 1, the NMOS transistor is off, and the output is maintained at V_OH = 5V by the PMOS device.

Similarly, for an input voltage greater than (V_DD - | V_TP | )(4 V) in region 5, the PMOS device is off, and the output is maintained at V_0L = 0V by the NMOS transistor. In region 2, the NMOS transistor is saturated, and the PMOS transistor is in the linear region. In region 3, both transistors are saturated. The boundary between regions 2&3 defined by the boundary between the saturation and linear region of operation for the PMOS transistor. Saturation of the PMOS device requires:

Table 3.2 Regions of operation of transistors in a symmetrical CMOS inverter

In a similar manner, the boundary between regions 3 and 4 is defined by saturation of the NMOS device:

 

In region 4, the voltage place the NMOS transistor in the linear region, and the PMOS transistor remains saturated. Finally, for the input voltage near V_DD/2   (region 3), both transistors are operating in the saturation region.

By using small channel length, produce increase in cut – off frequency so delay time decreased and this increase speed of operation.

 

Also me advantages of using small channel length:

1- decreasing tsohreshold voltage

2- decreasing supply voltage

3- decreasing palter dissipation

References

" Inverter " !